Peripheral Component Interconnect express (PCIe) (as described, for example, in The PCI Express Base Specification of the PCI Special Interest Group, Revision 3.0 published Nov. 18, 2010) describes an interconnection standard for coupling peripheral devices to a host computing system. The inbound data on a PCI express (PCIe) link is of serial form, running at a high clock frequency. The digital logic on the respective host system runs at a magnitude of half or more of that clock frequency. Before the data can be handed over to the digital logic, it is required to be converted to a parallel data format so that digital logic running at a lower clock frequency can handle all the incoming data. This serial-to-parallel conversion is done using a Serial In Parallel Out or Serial-To-Parallel Converter (SIPO).
A SIPO employs a serial shift register to implement the control logic required to load the serial data internally using the high clock frequency. System errors, such as clock glitches resulting from noise or system initialization processes, can render the serial shift register inoperable, which would mandate a system reset for re-initializing the PCIe link. What is needed is self-correction logic for serial-to-parallel converters, such as the above described converters used in PCIe links.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.